1. The Field of the Invention
The present invention relates to semiconductor device packages. More particularly, the present invention relates to modified bus bar structures on lead frames of semiconductor device packages.
2. The Relevant Technology
The advancement of microprocessing technology has resulted in decreases in the physical size dimensions of semiconductor devices such as integrated circuit dies or chips. Such dimensional decreases requires corresponding decreases in the dimensions of semiconductor device packages, including a reduction in the size of lead frames and leads used in such packages.
In many semiconductor devices, a lead called a "bus bar" is used to distribute operating voltages to several contact areas on the semiconductor device, and to provide a ground bus to individual contact areas. The bus bar serves as an inner lead for supplying a power supply voltage (Vcc) and a reference voltage (Vss), or a ground, to the semiconductor chip. The bus bar is generally posited so as to traverse the perimeter of the chip, and the bus bar is usually in the same general location or position as the inner lead finger tips. The bus bar can be connected to any point on the chip by short distance wire bonding to supply a voltage. Thus, the bus bar can be effectively employed to reduce noise and increase processing speed.
If the bus bar extends the length of the semiconductor device, the bonding wires between the lead fingers and the contact areas of the semiconductor chip must extend over the bus bar to provide electrical contact between the lead fingers and the contact areas. A problem that occurs in forming such semiconductor devices is that the bonding wires extending over the bus bar connecting the chip with the lead fingers can undesirably contact the bus bar, resulting in short circuiting between the bus bar and the bonding wires. For example, the bonding wires may fall or may be laterally pushed and deformed by a mechanical impact during the assembly process, or by the weight of such wires, resulting in undesirable contact. In addition, undesired contact of bonding wires may result from bonding wire sweep during the injection molding process from the pressure of an injected encapsulating material. The encapsulating material can move the delicate bonding wires which may, in turn, cause undesirable contact with the bus bar or other bonding wires, and thereby cause a short circuit.
If bonding wires are wired so as to form a larger loop in order to avoid contact with a bus bar, the wires become longer, thus increasing manufacturing costs. Furthermore, larger looping of bonding wires makes it more difficult to reduce the size and thickness of semiconductor devices.
In an attempt to solve the above problems, various techniques have been proposed for preventing short-circuiting due to the contact of two bonding wires or a bonding wire and a bus bar.
In U.S. Pat. No. 5,585,667 Asanasavest, an integrated circuit package is disclosed in which a lead frame has closely spaced leads patterned in such a way that one or more bonding wires must cross over another lead in order to be bonded to its associated lead. The lead frame is modified in various ways such that the likelihood of electrical contact between the bonding wires and leads crossed over by the bonding wires is reduced. In one embodiment, a depression is formed on the advance lead such that additional clearance is created between the bonding wires and the adjacent lead, thus reducing the likelihood of electrical contact. In another embodiment, a stepped depression is formed on a lead at the point where the bonding wire bonds to the lead. The walls of the depression cause the inclination of the bonding wire to be at an increased incline such that additional clearance is created between the bonding wire and the adjacent leads to reduce the likelihood of electrical contact.
In another semiconductor device disclosed in U.S. Pat. No. 5,592,020 to Nakao et al., leads such as a pair of bus bars have alternating offset projections. In one embodiment, an elongated portion of one of the bus bars, excluding the bonding projections on the bus bar, is pushed downward away from the bonding wires. Consequently, the elongated portion excluding the projections is positioned lower than the surface of the bonding areas provided on the projections.
In U.S. Pat. No. 5,532,189 to Kiyono, recessed bus bar regions are etched in an elongated bus bar to accommodate location of bonding wires which couple the chip pads and associated inner leads for a lead-on-chip (LOC) semiconductor device. Fillets are formed of insulative adhesive material up about the bus bar region sides to thereby engage the bonding wires to prevent contact between the wires and the bus bar. In addition, bus bars have been upset or positioned above the die in LOC devices.
The above approaches are disadvantageous as being overly complicated and expensive. Accordingly, there is a need for improved bus bar structures that overcome or avoid the above problems.